Component Library

Primitive Catalog

Ready-to-use building blocks organized by category. Each component is fully tested and synthesizable.

Category	Components	Description
Logic Gates	AND, OR, XOR, NOT, NAND, NOR, XNOR	Basic combinational logic, parameterized width
Multiplexers	Mux2, Mux4, MuxN	2-input, 4-input, and N-input select
Arithmetic	Adder, Subtractor, Comparator, Shifter	Parameterized width arithmetic units
Flip-Flops	DFF, DFFE, DFFR, DFFER	D flip-flop with enable and reset variants
Registers	Register, ShiftRegister, LFSR	Multi-bit storage with load, shift, feedback
Counters	Counter, UpDownCounter, RingCounter	Configurable width, wrap, and direction
Memory	RAM, ROM, RegisterFile	Configurable depth and width storage
ALU	SimpleALU, ALU	Arithmetic logic units with selectable ops

Usage Patterns

Instantiate and wire library components directly into your design. All components support parameterized widths.

using_primitives.rb

class Datapath < RHDL::Sim::Component
  input  :clk, :rst
  input  :a, :b, width: 8
  input  :op, width: 2
  output :result, width: 8

  component :alu,
    SimpleALU, width: 8

  component :out_reg,
    Register, width: 8

  wire :alu, :a => :a
  wire :alu, :b => :b
  wire :alu, :op => :op
  wire :out_reg, :d => :alu.result
  wire :result => :out_reg.q
end

Compose primitives into larger building blocks. A register file uses individual registers and a decoder.

register_file.rb

class RegFile8x8 < RHDL::Sim::Component
  input  :clk, :we
  input  :rd_addr, width: 3
  input  :wr_addr, width: 3
  input  :wr_data, width: 8
  output :rd_data, width: 8

  8.times do |i|
    component "r#{i}",
      Register, width: 8
  end

  component :rd_mux,
    MuxN,
    inputs: 8, width: 8
end