Multi-level circuit visualization in SVG, PNG, and DOT formats. See your hardware at any abstraction level, from high-level block diagrams to individual gates.
| Format | Type | Best For | Scalability |
|---|---|---|---|
| SVG | Vector | Documentation, web embedding, zoom-friendly viewing | Unlimited resolution |
| PNG | Raster | Quick previews, presentations, reports | Fixed resolution |
| DOT | Graph description | Custom rendering with Graphviz, CI pipelines | Text-based, any renderer |
CIRCT generates diagrams at three abstraction levels. Choose the right level for your needs.
Hierarchical view shows component boundaries and interconnections as labeled blocks with port connections.
cpu = CPU6502.new
cpu.diagram(
level: :hierarchical,
format: :svg,
output: "cpu_blocks.svg"
)
RTL view shows registers, multiplexers, and arithmetic operators matching the source abstraction.
alu = SimpleALU.new
alu.diagram(
level: :rtl,
format: :svg,
output: "alu_rtl.svg"
)
Generate diagrams in all formats at once, or target a specific abstraction level with custom options.
counter = Counter.new
# Generate all three formats
counter.diagram(format: :svg, output: "counter.svg")
counter.diagram(format: :png, output: "counter.png")
counter.diagram(format: :dot, output: "counter.dot")
# Gate-level view after synthesis
netlist = counter.synthesize(target: :gates)
netlist.diagram(
format: :svg,
output: "counter_gates.svg",
show_labels: true,
color_by: :gate_type
)