RTL simulation verifies your design at the register-transfer level — the same abstraction you write in. It is the fastest feedback loop during development.
Running RTL Simulation
rhdl simulate lib/counter.rb --level rtlOr programmatically in Ruby:
dut = Counter.new
dut.reset!
dut.enable = 1
10.times do |cycle|
dut.tick!
puts "Cycle #{cycle}: count = #{dut.count}"
endSimulation Backends
RTL simulation can use different backends:
- Ruby interpreter — slowest, but easiest to debug with
binding.pry - Rust native — compiled to native code for fast execution
- WASM — compiled to WebAssembly for browser-based simulation
Waveform Output
Capture signal traces in VCD format for viewing in GTKWave or other waveform viewers:
dut.trace_to("output.vcd") do
1000.times { dut.tick! }
endComparison with Gate-Level
RTL simulation is faster because it operates on higher-level abstractions. Use it for functional verification. Switch to gate-level simulation when you need to verify timing and synthesis correctness.